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EMI4192
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low
a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per
the IEC61000 ? 4 ? 2 waveform. Since the IEC61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones
or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor
has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD
pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these screenshots and how to interpret them please refer to On Semiconductor
Application Notes AND8307/D and AND8308/D.
IEC61000 ? 4 ? 2 Spec.
Test First Peak
Voltage Current
Level (kV) (A)
Current at
30 ns (A)
Current at
60 ns (A)
I peak
100%
90%
IEC61000 ? 4 ? 2 Waveform
1
2
7.5
4
2
2
3
4
4
6
8
15
22.5
30
8
12
16
4
6
8
I @ 30 ns
I @ 60 ns
10%
t P = 0.7 ns to 1 ns
ESD Gun
TVS
Oscilloscope
50 W
50 W
Cable
Figure 11. Diagram of ESD Test Setup
100
90
80
70
60
50
40
30
20
10
t r
t P
PEAK VALUE I RSM @ 8 m s
PULSE WIDTH (t P ) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 m s
HALF VALUE I RSM /2 @ 20 m s
0
0
20
40
60
80
t, TIME ( m s)
Figure 12. 8 x 20 m s Pulse Waveform
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